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1 LT3471 sn3471 3471fs dual 1.3a, 1.2mhz boost/inverter in 3mm 3mm dfn 1.2mhz switching frequency low v cesat switches: 330mv at 1.3a high output voltage: up to 40v wide input range: 2.4v to 16v inverting capability 5v at 630ma from 3.3v input 12v at 320ma from 5v input C12v at 200ma from 5v input uses tiny surface mount components low shutdown current: < 1 a low profile (0.75mm) 10-lead 3mm 3mm dfn package oled driver organic led power supply digital cameras white led power supply cellular phones medical diagnostic equipment local 5v or 12v supply tft-lcd bias supply xdsl power supply the lt ? 3471 dual switching regulator combines two 42v, 1.3a switches with error amplifiers that can sense to ground providing boost and inverting capability. the low v cesat bipolar switches enable the device to deliver high current outputs in a small footprint. the LT3471 switches at 1.2mhz, allowing the use of tiny, low cost and low profile inductors and capacitors. high inrush current at start-up is eliminated using the programmable soft-start function, where an external rc sets the current ramp rate. a constant frequency current mode pwm architecture results in low, predictable output noise that is easy to filter. the LT3471 switches are rated at 42v, making the device ideal for boost converters up to 40v as well as sepic and flyback designs. each channel can generate 5v at up to 630ma from a 3.3v supply, or 5v at 510ma from four alkaline cells in a sepic design. the device can be config- ured as two boosts, a boost and inverter or two inverters. the LT3471 is available in a low profile (0.75mm) 10-lead 3mm 3mm dfn package. oled driver efficiency features descriptio u applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. 4.7k control 1 3471 ta01 0.33 f 10 f 4.7k control 2 0.33 f v in shdn/ss1 fb1n sw1 sw2 LT3471 10 h 15 h gnd fb1p v in 3.3v fb2p fb2n v ref 0.1 f 4.7 f v out1 7v 350ma v out2 C7v 250ma 75pf 15k 90.9k 15k 105k 1 f shdn/ss2 v in v in 10 f 2.2 h i out (ma) 0 efficiency (%) 75 80 85 400 3471 ta01b 70 65 50 100 200 300 60 55 95 90 v out1 = 7v v out1 = C7v
2 LT3471 sn3471 3471fs parameter conditions min typ max units minimum operating voltage 2.1 2.4 v reference voltage 0.991 1.000 1.009 v 0.987 1.013 v reference voltage current limit (note 3) 1 1.4 ma reference voltage load regulation 0ma i ref 100 a (note 3) 0.1 0.2 %/100 a reference voltage line regulation 2.6v v in 16v 0.03 0.08 %/v error amplifier offset transition from not switching to switching, v fbp = v fbn = 1v 2 3mv fb pin bias current (note 3) 60 100 na quiescent current v shdn = 1.8v, not switching 2.5 4 ma quiescent current in shutdown v shdn = 0.3v, v in = 3v 0.01 1 a switching frequency 1 1.2 1.4 mhz maximum duty cycle 90 94 % 86 % minimum duty cycle 15 % switch current limit at minimum duty cycle 1.5 2.05 2.6 a at maximum duty cycle (note 4) 0.9 1.45 2.0 a switch v cesat i sw = 0.5a (note 5) 150 250 mv switch leakage current v sw = 5v 0.01 1 a shdn/ss input voltage high 1.8 v shdn input voltage low quiescent current 1 a 0.3 v shdn pin bias current v shdn = 3v, v in = 4v 22 36 a v shdn = 0v 0 0.1 a (note 1) v in voltage .............................................................. 16v sw1, sw2 voltage ....................................C 0.4v to 42v fb1n, fb1p, fb2n, fb2p voltage ....... 12v or v in C 1.5v shdn/ss1, shdn/ss2 voltage .............................. 16v v ref voltage ........................................................... 1.5v maximum junction temperature ......................... 125 c operating temperature range (note 2) .. C 40 c to 85 c storage temperature range ................. C 65 c to 125 c the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = v shdn = 3v unless otherwise noted. order part number LT3471edd dd part marking lbhm t jmax = 125 c, ja = 43 c/ w, jc = 3 c/ w exposed pad (pin 11) is gnd must be soldered to pcb electrical characteristics package/order i for atio uu w absolute axi u rati gs w ww u consult ltc marketing for parts specified with wider operating temperature ranges. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LT3471e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. top view 11 dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 sw1 shdn/ss1 v in shdn/ss2 sw2 fb1n fb1p v ref fb2p fb2n note 3: current flows out of the pin. note 4: see typical performance characteristics for guaranteed current limit vs duty cycle. note 5: v cesat is 100% tested at wafer level.
3 LT3471 sn3471 3471fs typical perfor a ce characteristics uw quiescent current vs temperature v ref voltage vs temperature v ref voltage vs v ref current shdn/ss current vs shdn/ss voltage current limit vs duty cycle switch saturation voltage vs switch current oscillator frequency vs temperature start-up waveform (figure 2 circuit) peak switch current vs shdn/ss voltage temperature ( c) C50 C25 1.6 quiescent current (ma) 2.0 2.6 0 50 75 3471 g01 1.8 2.4 2.2 25 100 125 temperature ( c) C50 C25 0.990 v ref (v) 1.000 1.010 0 50 75 3471 g02 0.995 1.005 25 100 125 v ref voltage 100mv/div v ref current 200 a/div 3741 g03 shdn/ss current 20 v/div shdn/ss voltage 1v/div 3741 g04 v in = 3.3v v in > v shdn/ss duty cycle (%) 0 current limit (a) 1.2 1.6 2.2 2.0 80 3471 g05 0.8 0.4 1.0 1.4 1.8 0.6 0.2 0 20 40 60 100 typical guaranteed t a = 25 c sw current (a) 0 v cesat (mv) 800 700 600 500 400 300 200 100 0 1.6 3471 g06 0.4 0.8 1.2 2.0 1.4 0.2 0.6 1.0 1.8 90 c 25 c temperature ( c) C50 1.00 frequency (mhz) 1.05 1.15 1.20 1.25 1.50 1.35 0 50 75 3471 g07 1.10 1.40 1.45 1.30 C25 25 100 125 v shdn/ss (v) 0 switch current (a) 1.2 1.6 2.0 1.6 3471 g08 0.8 0.4 1.0 1.4 1.8 0.6 0.2 0 0.4 0.2 0.8 0.6 1.2 1.4 1.8 1 2.0 t a = 25 c i supply 1a/div v out1 2v/div v out2 5v/div control 1 and 2 5v/div 0.5ms/div 3471 g09
4 LT3471 sn3471 3471fs uu u pi fu ctio s fb1n (pin 1): negative feedback pin for switcher 1. connect resistive divider tap here. minimize trace area at fb1n. set v out = v fb1p (1 + r1/r2), or connect to ground for inverting topologies. fb1p (pin 2): positive feedback pin for switcher 1. con- nect either to v reg or a divided down version of v reg , or connect to a resistive divider tap for inverting topologies. v ref (pin 3): 1.00v reference pin. can supply up to 1ma of current. do not pull this pin high. must be locally bypassed with no less than 0.01 f and no more than 1 f . a 0.1 f ceramic capacitor is recommended. use this pin as the positive feedback reference or connect a resistor divider here for a smaller reference voltage. fb2p (pin 4): same as fb1p but for switcher 2. fb2n (pin 5): same as fb1n but for switcher 2. sw2 (pin 6): switch pin for switcher 2 (collector of internal npn power switch). connect inductor/diode here block diagra w and minimize the metal trace area connected to this pin to minimize emi. shdn/ss2 (pin 7): shutdown and soft-start pin. tie to 1.8v or more to enable device. ground to shut down. soft- start function is provided when the voltage at this pin is ramped slowly to 1.8v with an external rc circuit. v in (pin 8): input supply. must be locally bypassed. shdn/ss1 (pin 9): same as shdn/ss2 but for switcher 1. note: taking either shdn/ss pin high will enable the part. each switcher is individually enabled with its respective shdn/ss pin. sw1 (pin 10): same as sw2 but for switcher 1. exposed pad (pin 11): ground. connect directly to local ground plane. this ground plane also serves as a heat sink for optimal thermal performance. C + C + rq s 0.01 ? sw1 driver 10 fb1n shdn/ss1 1 9 fb1p 2 C + ramp generator 1.00v reference level shifter r c c c 1.2mhz oscillator gnd gnd q1 a2 a1 v in v ref 8 3 C + C + rq s 0.01 ? sw2 driver 6 11 fb2n shdn/ss2 5 7 fb2p 4 C + ramp generator level shifter r c c c 3471 f01 q2 a4 a3 figure 1. block diagram
5 LT3471 sn3471 3471fs operatio u the LT3471 uses a constant frequency, current mode control scheme to provide excellent line and load regula- tion. refer to the block diagram. at the start of each oscillator cycle, the sr latch is set, which turns on the power switch, q1 (q2). a voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator a2 (a4). when this voltage exceeds the level at the negative input of a2 (a4), the sr latch is reset, turning off the power switch q1 (q2). the level at the negative input of a2 (a4) is set by the error amplifier a1 (a3) and is simply an amplified version of the difference between the negative feedback voltage and the positive feedback voltage, usually tied to the reference voltage v reg . in this manner, the error amplifier sets the correct peak current level to keep the output in regulation. if the error amplifiers output increases, more current is deliv- ered to the output. similarly, if the error decreases, less current is delivered. each switcher functions indepen- dently but they share the same oscillator and thus the switchers are always in phase. enabling the part is done by taking either shdn/ss pin above 1.8v. disabling the part is done by grounding both shdn/ss pins. the soft-start feature of the LT3471 allows for clean start-up conditions by limiting the amount of voltage rise at the output of comparator a1 and a2, which in turn limits the peak switching current. the soft-start feature for each switcher is enabled by slowly ramping that switchers shdn/ss pin, using an rc network, for example. typical resistor and capacitor values are 0.33 f and 4.7k ? , allowing for a start-up time on the order of milliseconds. the LT3471 has a current limit circuit not shown in the block diagram. the switch current is constantly monitored and not allowed to exceed the maximum switch current (typically 1.6a). if the switch current reaches this value, the sr latch is reset regardless of the state of the comparator a2 (a4). also not shown in the block diagram is the thermal shutdown circuit. if the temperature of the part exceeds approxi- mately 160 c, both latches are reset regardless of the state of comparators a2 and a4. the current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the LT3471. applicatio n s i n for m atio n wu u u duty cycle the typical maximum duty cycle of the LT3471 is 94%. the duty cycle for a given application is given by: dc vvv vvv out d in out d cesat = + + ||||C|| ||||C| | where v d is the diode forward voltage drop and v cesat is in the worst case 330mv (at 1.3a) the LT3471 can be used at higher duty cycles, but it must be operated in the discontinuous conduction mode so that the actual duty cycle is reduced. setting output voltage setting the output voltage depends on the topology used. for normal noninverting boost regulator topologies: vv r r out fbp =+ ? ? ? ? ? ? 1 1 2 where v fbn is connected between r1 and r2 (see the typical applications section for examples). select values of r1 and r2 according to the following equation: rr v v out ref 12 1 = ? ? ? ? ? ? C a good value for r2 is 15k which sets the current in the resistor divider chain to 1.00v/15k = 67 a. v fbp is usually just tied to v ref = 1.00v, but v fbp can also be tied to a divided down version of v ref or some other voltage as long as the absolute maximum ratings for the feedback pins are not exceeded (see absolute maximum ratings). for inverting topologies, v fbn is tied to ground and v fbp is connected between r1 and r2. r2 is between v fbp and
6 LT3471 sn3471 3471fs applicatio n s i n for m atio n wu u u v ref and r1 is between v fbp and v out (see the applica- tions section for examples). in this case: vv r r out ref = ? ? ? ? ? ? 1 2 select values of r1 and r2 according to the following equation: rr v v out ref 12 = ? ? ? ? ? ? a good value for r2 is 15k, which sets the current in the resistor divider chain to 1.00v/15k = 67 a. switching frequency and inductor selection the LT3471 switches at 1.2 mhz, allowing for small valued inductors to be used. 4.7 h or 10 h will usually suffice. choose an inductor that can handle at least 1.4a without saturating, and ensure that the inductor has a low dcr (copper-wire resistance) to minimize i 2 r power losses. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor only carries one half of the total switch current. for better efficiency, use similar valued inductors with a larger volume. many different sizes and shapes are available from various manufactur- ers. choose a core material that has low losses at 1.2 mhz, such as ferrite core. table 1. inductor manufacturers sumida (847) 956-0666 www.sumida.com tdk (847) 803-6100 www.tdk.com murata (714) 852-2001 www.murata.com soft-start and shutdown features to shut down the part, ground both shdn/ss pins. to shut down one switcher but not the other one, ground that switchers shdn/ss pin. the soft-start feature provides a way to limit the inrush current drawn from the supply upon start-up. to use the soft-start feature for either switcher, slowly ramp up that switchers shdn/ss pin. the rate of voltage rise at the output of the switchers comparator (a1 or a3 for switcher 1 or switcher 2 respectively) tracks the rate of voltage rise at the shdn/ss pin once the shdn/ss pin has reached about 1.1v. the soft-start function will go away once the voltage at the shdn/ss pin exceeds 1.8v. see the peak switch current vs shdn/ss voltage graph in the typical performance characteristics section. the rate of voltage rise at the shdn/ss pin can easily be controlled with a simple rc network connected between the control signal and the shdn/ss pin. typical values for the rc network are 4.7k ? and 0.33 f, giving start-up times on the order of milliseconds. this rc time constant can be adjusted to give different start-up times. if different values of resistance are to be used, keep in mind the shdn/ss current vs shdn/ss voltage graph along with the peak switch current vs shdn/ss voltage graph, both found in the typical performance characteristics section. the im- pedance looking into the shdn/ss pin depends on whether the shdn/ss is above or below v in . normally shdn/ss will not be driven above v in , and thus the impedance looks like 100k ? in series with a diode. if the voltage of the shdn/ss pin is above v in , the impedance looks more like 50k ? in series with a diode. this 100k ? or 50k ? imped- ance can have a slight effect on the start-up time if you choose the r in the rc soft-start network too large. another consideration is selecting the soft-start time so that the soft-start feature is dominated by the rc network and not the capacitor on v ref . (see v ref voltage reference section of the applications information for details.) capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multi-layer ceramic capacitors are an excellent choice, as they have extremely low esr and are available in very small packages. x5r dielectrics are preferred, followed by x7r, as these materials retain the capacitance over wide voltage and temperature ranges. a 4.7 f to 15 f output capacitor is sufficient for most applications, but systems with very low output currents may need only a 1 f or 2.2 f output capacitor. solid tantalum or os-con capacitors can be used, but they will occupy more board area than a ceramic and will have a higher esr. always use a capacitor with a sufficient voltage rating. ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as close as possible to the LT3471. a 4.7 f to 10 f input capacitor is
7 LT3471 sn3471 3471fs applicatio n s i n for m atio n wu u u supply current of figure 2 during start-up without soft-start rc network v out1 2v/div i supply 0.5a/div 0.1ms/div 3471 f02b supply current of figure 2 during start-up with soft-start rc network r ss1 4.7k r ss2 4.7k control 1 3471 f02 c ss1 0.33 f c ss2 0.33 f 10 f v in 2.6v to 4.2v li-ion shdn/ss1 fb1n 9 0v 1.8v control 2 0v 1.8v 8 7 sw1 sw2 LT3471 l2 10 h l3 15 h gnd fb1p v in fb2p fb2n v ref c2 0.1 f c3 4.7 f c pl 33pf v out1 7v v out2 C7v c1, c2: x5r or x7r 6.3v c3, c4: x5r or x7r 10v c5: xr5 or x7r 16v c pl : optional d1, d2: on semiconductor mbrm-120 l1: sumida cr43-2r2 l2: sumida cdrh4d18-100 l3: sumida cdrh4d18-150 c6 75pf r2 15k r3 90.9k r4 15k r1 105k c5 1 f shdn/ss2 v in 10 1 2 3 5 4 11 6 v in c4 10 f d2 l1 2.2 h d1 figure 2. li-ion oled driver sufficient for most applications. table 2 shows a list of several ceramic capacitor manufacturers. consult the manufacturers for detailed information on their entire selection of ceramic parts. table 2. ceramic capacitor manufacturers taiyo yuden (408) 573-4150 www.t-yuden.com avx (803) 448-9411 www.avxcorp.com murata (714) 852-2001 www.murata.com the decision to use either low esr (ceramic) capacitors or the higher esr (tantalum or os-con) capacitors can affect the stability of the overall system. the esr of any capacitor, along with the capacitance itself, contributes a zero to the system. for the tantalum and os-con capaci- tors, this zero is located at a lower frequency due to the higher value of the esr, while the zero of a ceramic capaci- tor is at a much higher frequency and can generally be ignored. a phase lead zero can be intentionally introduced by placing a capacitor (c pl ) in parallel with the resistor (r3) between v out and v fb as shown in figure 2. the frequency of the zero is determined by the following equation. v out1 2v/div i supply 0.5a/div 0.2ms/div 3471 f02c
8 LT3471 sn3471 3471fs ?= z pl rc 1 23 ?? by choosing the appropriate values for the resistor and capacitor, the zero frequency can be designed to improve the phase margin of the overall converter. the typical target value for the zero frequency is between 35khz to 55khz. figure 3 shows the transient response of the step- up converter from figure 2 without the phase lead capaci- tor c pl . although adequate for many applications, phase margin is not ideal as evidenced by 2-3 bumps in both the output voltage and inductor current. a 33pf capacitor for c pl results in ideal phase margin, which is revealed in figure 4 as a more damped response and less overshoot. applicatio n s i n for m atio n wu u u figure 3. transient response of figure 2? step-up converter without phase lead capacitor figure 4. transient response of figure 2? step-up converter with 33pf phase lead capacitor 50 s/div 3471 f04 load current 100ma/div ac coupled v out 200mv/div ac coupled 50 s/div 3471 f03 i l1 0.5a/div ac coupled load current 100ma/div ac coupled v out 200mv/div ac coupled i l1 0.5a/div ac coupled v reg voltage reference pin 3 of the LT3471 is a bandgap voltage reference that has been divided down to 1.00v and buffered for external use. this pin must be bypassed with at least 0.01 f and no more than 1 f. this will ensure stability as well as reduce the noise on this pin. the buffer has a built-in current limit of at least 1ma (typically 1.4ma). this not only means that you can use this pin as an external reference for supple- mental circuitry, but it also means that it is possible to provide a soft-start feature if this pin is used as one of the feedback pins for the error amplifier. normally the soft- start time will be dominated by the rc time constant discussed in the soft-start and shutdown section. how- ever, because of the finite current limit of the buffer for the v reg pin, it will take some time to charge up the bypass capacitor. during this time, the voltage at the v reg pin will ramp up, and this action provides an alternate means for soft-starting the circuit. if the largest recommended by- pass capacitor is used, 1 f, the worst-case (longest) soft- start function that would be provided from the v ref pin is: 1100 10 10 = fv ma ms ?. . . choose the rc network such that the soft-start time is longer than this time, or choose a smaller bypass capaci- tor for the v ref pin (but always larger than 0.01 f) so that the rc network dominates the soft-starting of the LT3471. the voltage at the v ref pin can also be divided down and used for one of the feedback pins for the error amplifier. this is especially useful in led driver applications, where the current through the leds is set using the voltage reference across a sense resistor in the led chain. using a smaller or divided down reference leads to less wasted power in the sense resistor. see the typical applications section for an example of led driving applications. diode selection a schottky diode is recommended for use with the LT3471. for high efficiency, a diode with good thermal character- istics at high currents should be used such as the on
9 LT3471 sn3471 3471fs applicatio n s i n for m atio n wu u u semiconductor mbrm120. this is a 20v diode. where the switch voltage exceeds 20v, use the mbrm140, a 40v diode. these diodes are rated to handle an average for- ward current of 1.0a. in applications where the average forward current of the diode is less than 0.5a, use the philips pmeg 2005, 3005, or 4005 (a 20v, 30v or 40v diode, respectively). layout hints the high speed operation of the LT3471 demands careful attention to board layout. you will not get advertised performance with careless layout. figure 5 shows the recommended component placement. compensation?heory like all other current mode switching regulators, the LT3471 needs to be compensated for stable and efficient operation. two feedback loops are used in the LT3471: a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 6 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by the equivalent transconductance amplifier g mp . g mp acts as a current source where the output current is proportional to the v c voltage. note that the maximum output current of g mp is finite due to the current limit in the ic. from figure 6, the dc gain, poles and zeroes can be calculated as follows: figure 5. suggested layout showing a boost on sw1 and an inverter on sw2. note the separate ground returns for all high current paths (using a multilayer board) 10 gnd gnd shdn/ss1 9 8 7 shdn/ss2 fb1n r4 r2 r3 fb1p v out1 r1 c2 3471 f05 c3 c ss1 c ss2 r ss1 r ss2 c1 ? ? c4 d2 v out1 v out2 sw1 sw2 c5 d1 l1 l2 l3 v out2 fb2p fb2n v ref 6 1 2 3 4 5 LT3471 pin 11 gnd v cc gnd gnd gnd control 1 control 2 output pole: p1= 2 2? ?r error amp pole: p2 = 1 2? ?r error amp zero: z1= 1 2? ?r dc gain: a = v v esr zero: rhp zero: z3 = high frequency pole: p3 > l o c ref out = = ? ? ? ????? ?? ? ? ?? ? : ? c c c grgr z rc vr vl f phase lead zero z out c c ma o mp l esr out in l out s 1 2 2 1 2 2 3 4 1 2 2 2 ?? : ?? ? ? rc phase lead pole p c rr rr pl pl 1 4 1 2 12 12 = +
10 LT3471 sn3471 3471fs C + C + g ma r c r o r2 c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out divided by i load(max) r o : output resistance of g ma r1, r2: feedback resistor divider network r esr : output capacitor esr 3471 f06 r1 c out c pl r l r esr v out v c c c g mp 1.00v reference figure 6. boost converter equivalent model applicatio n s i n for m atio n wu u u the current mode zero is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. using the circuit of figure 2 as an example, table 3 shows the parameters used to generate the bode plot shown in figure 7. table 3. bode plot parameters parameter value units comment r l 20 ? application specific c out 4.7 f application specific r esr 10 m ? application specific r o 0.9 m ? not adjustable c c 90 pf not adjustable c pl 33 pf adjustable r c 55 k ? not adjustable r1 90.9 k ? adjustable r2 15 k ? adjustable v out 7 v application specific v in 3.3 v application specific g ma 50 mho not adjustable g mp 9.3 mho not adjustable l 2.2 h application specific f s 1.2 mhz not adjustable from figure 7, the phase is C115 when the gain reaches 0db giving a phase margin of 65 . this is more than adequate. the crossover frequency is 50khz. figure 7. bode plot of 3.3v to 7v application frequency (hz) 0 gain (db) phase (deg) 60 70 C10 C20 50 20 40 30 10 100 10k 100k 1m 3471 f07 C30 C350 C50 0 C100 C250 C150 C200 C300 C400 1k gain phase
11 LT3471 sn3471 3471fs typical applicatio s u r ss1 4.7k r ss2 4.7k control 1 3471 ta02 c ss1 0.33 f c ss2 0.33 f c1 10 f v in 2.6v to 4.2v li-ion shdn/ss1 fb1n 9 0v 1.8v control 2 0v 1.8v 8 7 sw1 sw2 LT3471 l2 15 h l3 15 h gnd fb1p v in fb2p fb2n v ref c2 0.1 f c3 4.7 f c6 33pf v out1 7v 500ma when v in = 4.2v 350ma when v in = 3.3v 250ma when v in = 2.6v v out2 C7v to C4v C7v when v control = 0v C4v when v control = 1 C7v, 300ma when v in = 4.2v C7v, 250ma when v in = 3.3v C7v, 200ma when v in = 2.6v c1, c2: x5r or x7r 6.3v c3, c4: x5r or x7r 10v c5: xr5 or x7r 16v c6: optional d1, d2: on semiconductor mbrm-120 l1: sumida cr43-2r2 l2: sumida cdrh4d18-100 l3: sumida cdrh4d18-150 c6 75pf r2 15k r5 20k r6 10k r3 90.9k r4 15k r1 105k c5 1 f shdn/ss2 v in 10 1 2 3 5 4 11 6 v in c4 10 f d2 l1 2.2 h d1 v control 0v to 1v li-ion oled driver i out (ma) 0 50 efficiency (%) 55 65 70 75 200 400 500 95 3471 ta02b 60 100 300 80 85 90 v out = 7v v in = 4.2v v in = 4.2v v in = 3.3v v in = 3.3v v in = 2.6v v in = 2.6v v out = C7v li-ion oled driver efficiency
12 LT3471 sn3471 3471fs typical applicatio s u single li-ion cell to 5v, 12v boost converter r ss1 4.7k r ss2 4.7k control 1 3471 ta03 c ss1 0.33 f c ss2 0.33 f c1 4.7 f v in 2.6v to 4.2v shdn/ss1 fb1n 9 ov 1.8v 1.8v 0v control 2 8 7 sw1 sw2 LT3471 l2 6.8 h gnd fb1p v in fb2n fb2p v ref c2 0.1 f c3 10 f c5 100pf c6 220pf v out1 5v 900ma if v in = 4.2v 630ma if v in = 3.3v 425ma if v in = 2.6v v out2 12v 300ma if v in = 4.2v 210ma if v in = 3.3v 145ma if v in = 2.6v c1-c3: x5r or x7r 6.3v c4: x5r or x7r 16v d1, d2: on semiconductor mbrm-120 l1: sumida cr43-3r3 l2: sumida cr43-6r8 r1 20k r2 4.99k r3 54.9k r4 4.99k shdn/ss2 v in 10 1 2 3 4 5 11 6 v in c4 10 f l1 3.3 h d1 d2
13 LT3471 sn3471 3471fs typical applicatio s u li-ion 20 white led driver r ss1 4.7k r ss2 4.7k 3471 ta04 c ss1 0.33 f c ss2 0.33 f c1 4.7 f v in 2.6v to 4.2v shdn/ss1 fb1n 9 8 7 sw1 sw2 LT3471 l2 2.2 h gnd fb1p v in fb2n fb2p v ref c2 0.1 f r1 90.9k c3 0.22 f i out1 20ma c1, c2: x5r or x7r 6.3v c3, c4: x5r or x7r 50v d1, d2: on semiconductor mbrm-140 l1, l2: sumida cdrh2d-2r2 r2 10k 4.99 ? shdn/ss2 v in 10 1 2 3 4 5 11 6 v in c4 0.22 f l1 2.2 h d1 d2 i out2 20ma 10 white leds 10 white leds 4.99 ? control 1 ov 1.8v control 2 ov 1.8v
14 LT3471 sn3471 3471fs typical applicatio s u li-ion or 4-cell alkaline to 3.3v and 5v sepic r ss1 4.7k r ss2 4.7k 3471 ta05 c ss1 0.33 f c ss2 0.33 f c1 4.7 f v in 2.6v to 6.5v shdn/ss1 fb1n 9 8 7 sw1 sw2 LT3471 l3 10 h gnd fb1p v in fb2n fb2p v ref c2 0.1 f c4 15 f c7 56pf c8 56pf c3 4.7 f c5 10 f v out1 3.3v 640ma at v in = 6.5v 550ma at v in = 5v 470ma at v in = 4v 410ma at v in = 3.3v 340ma at v in = 2.6v v out2 5v 500ma at v in = 6.5v 420ma at v in = 5v 360ma at v in = 4v 300ma at v in = 3.3v 250ma at v in = 2.6v c1, c3, c5: x5r or x7r 10v c4, c6: x5r or x7r 6.3v d1, d2: on semiconductor mbrm-120 l1-l4: murata lqh43cn100k032 r1 34.8k l2 10 h r2 15k r3 60.4k r4 15k shdn/ss2 v in 10 1 2 3 4 5 11 6 v in c6 15 f l1 10 h d1 d2 l4 10 h control 1 ov 1.8v control 2 ov 1.8v
15 LT3471 sn3471 3471fs u package descriptio dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 LT3471 sn3471 3471fs lt/tp 0804 1k ?printed in usa ? linear technology corporation 2004 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments lt1611 550ma (i sw ), 1.4mhz, high efficiency micropower inverting v in : 1.1v to 10v, v out(max) = C34v, i q = 3ma, i sd < 1 a, dc/dc converter thinsot package lt1613 550ma (i sw ), 1.4mhz, high efficiency step-up v in : 0.9v to 10v, v out(max) = 34v, i q = 3ma, i sd < 1 a, dc/dc converter thinsot package lt1614 750ma (i sw ), 600khz, high efficiency micropower inverting v in : 1v to 12v, v out(max) = C24v, i q = 1ma, i sd < 10 a, dc/dc converter ms8, s8 packages lt1615/lt1615-1 300ma/80ma (i sw ), high efficiency step-up dc/dc converters v in = 1v to 15v, v out(max) = 34v, i q = 20 a, i sd < 1 a, thinsot package lt1617/lt1617-1 350ma/100ma (i sw ), high efficiency micropower inverting v in = 1.2v to 15v, v out(max) = C34v, i q = 20 a, i sd < 1 a, dc/dc converters thinsot package lt1930/lt1930a 1a (i sw ), 1.2mhz/2.2mhz, high efficiency v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2ma/5.5ma, step-up dc/dc converters i sd < 1 a, thinsot package lt1931/lt1931a 1a (i sw ), 1.2mhz/2.2mhz high efficiency micropower inverting v in = 2.6v to 16v, v out(max) = C34v, i q = 5.8ma, i sd < 1 a, dc/dc converters thinsot package lt1943 (quad) quad boost, 2.6a buck, 2.6a boost, 0.3a boost, 0.4a inverter v in = 4.5v to 22v, v out(max) = 40v, i q = 10 a, i sd < 35 a, 1.2mhz tft dc/dc converter tssop28e package lt1945 (dual) dual output, boost/inverter, 350ma (i sw ), constant off-time, v in = 1.2v to 15v, v out(max) = 34v, i q = 40 a, i sd < 1 a, high efficiency step-up dc/dc converter 10-lead ms package lt1946/lt1946a 1.5a (i sw ), 1.2mhz/2.7mhz, high efficiency v in : 2.45v to 16v, v out(max) = 34v, i q = 3.2ma, i sd < 1 a, step-up dc/dc converters ms8 package lt3436 3a (i sw ), 1mhz, 34v step-up dc/dc converter v in : 3v to 25v, v out(max) = 34v, i q = 0.9ma, i sd < 6 a, tssop16e package lt3462/lt3462a 300ma (i sw ), 1.2mhz/2.7mhz, high efficiency inverting v in = 2.5v to 16v, v out(max) = C38v, i q = 2.9ma, i sd < 1 a, dc/dc converters with integrated schottkys thinsot package lt3463/lt3463a dual output, boost/inverter, 250ma (i sw ), constant off-time, v in = 2.3v to 15v, v out(max) = 40v, i q = 40 a, i sd < 1 a, high efficiency step-up dc/dc converters with integrated dfn package schottkys lt3464 85ma (i sw ), high efficiency step-up dc/dc converter with v in = 2.3v to 10v, v out(max) = 34v, i q = 25 a, i sd < 1 a, integrated schottky and pnp disconnect thinsot package 5v to 12v dual supply boost/inverting converter 4.7k 4.7k 3471 ta06 0.33 f 0.33 f c1 4.7 f v in 5v shdn/ss1 fb1n 9 8 7 sw1 sw2 LT3471 l2 10 h c5 1 f gnd fb1p v in fb2n fb2p v ref c2 0.1 f c3 4.7 f c6 56pf v out1 12v 320ma v out2 C12v 200ma c1, c2: x5r or x7r 6.3v c3, c4: x5r or x7r 16v c5: x5r or x7r 25v d1, d2: on semiconductor mbrm-120 l1: sumida cr43-10 l2, l3: sumida cls63-10 r1 54.9k r2 4.99k r3 15k r4 182k shdn/ss2 v in 10 1 2 3 4 5 11 6 ? v in c4 4.7 f c7 56pf l1 10 h d1 d2 l3 10 h ? control 1 ov 1.8v control 2 ov 1.8v typical applicatio u

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